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Agilent HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J High Speed Digital Isolators Data Sheet
Features * +3.3V and +5V TTL/CMOS compatible * 3 ns max. pulse width distortion * 6 ns max. propagation delay skew * 15 ns max. propagation delay Description The HCPL-90xx and HCPL-09xx CMOS digital isolators feature high speed performance and excellent transient immunity specifications. The symmetric magnetic coupling barrier gives these devices a typical pulse width distortion of 2 ns, a typical propagation delay skew of 4 ns and 100 Mbaud data rate, making them the industry's fastest digital isolators. The single channel digital isolators (HCPL-9000/-0900) features an active-low logic output enable. The dual channel digital isolators are configured as unidirectional (HCPL-9030/-0930) and bidirectional (HCPL-9031/-0931), operating in full duplex mode making it ideal for digital fieldbus applications. The quad channel digital isolators are configured as unidirectional (HCPL-900J/-090J), two channels in one direction and two channels in opposite direction (HCPL-901J/-091J), and one channel in one direction and three channels in opposite direction (HCPL-902J/-092J). These high channel density make them ideally suited to isolating data conversion devices, parallel buses and peripheral interfaces. They are available in 8-pin PDIP, 8-pin Gull Wing, 8-pin SOIC packages, and 16-pin SOIC narrow-body and wide-body packages. They are specified over the temperature range of -40 C to +100 C. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by ESD. * High speed: 100 MBd * 15 kV/s min. common mode rejection * Tri-state output (HCPL-9000/-0900) * 2500 V RMS isolation * UL1577 and IEC 61010-1 approved
Applications * Digital fieldbus isolation * Multiplexed data transmission * Computer peripheral interface * High speed digital systems * Isolated data interfaces * Logic level shifting
Selection Guide Device Number
HCPL-9000 HCPL-0900 HCPL-9030 HCPL-0930 HCPL-9031 HCPL-0931 HCPL-900J HCPL-090J HCPL-901J HCPL-091J HCPL-902J HCPL-092J
Channel Configuration
Single Single Dual Dual Dual, Bi-Directional Dual, Bi-Directional Quad Quad Quad, 2/2, Bi-Directional Quad, 2/2, Bi-Directional Quad, 1/3, Bi-Directional Quad, 1/3, Bi-Directional
Package
8-pin DIP (300 Mil) 8-pin Small Outline 8-pin DIP (300 Mil) 8-pin Small Outline 8-pin DIP (300 Mil) 8-pin Small Outline 16-pin Small Outline, Wide Body 16-pin Small Outline, Narrow Body 16-pin Small Outline, Wide Body 16-pin Small Outline, Narrow Body 16-pin Small Outline, Wide Body 16-pin Small Outline, Narrow Body
Ordering Information Specify Part Number followed by Option Number (if desired). Examples: HCPL-90xx-xxx xxx: No option = 300 Mil PDIP-8 package, 50 units per tube. 300 = Gull Wing Surface Mount Option, 50 units per tube. 500 = Tape and Reel Packaging Option, 1000 units per reel. HCPL-09xx-xxx xxx: No option = SO-8 package, 100 units per tube. 500 = Tape and Reel Packaging Option, 1500 units per reel. HCPL-90xJ-xxx xxx: No option = Wide Body SOIC-16 package, 50 units per tube. 500 = Tape and Reel Packaging Option, 1000 units per reel. HCPL-09xJ-xxx xxx: No option = Narrow Body SOIC-16 package, 50 per tube. 500 = Tape and Reel Packaging Option, 1000 units per reel.
2
Pin Description Symbol
VDD1 VDD2 INX OUTX GND1 GND2 VOE NC
Functional Diagrams Single Channel
VDD1 IN1 NC GND1
1 8
Description
Power Supply 1
Galvanic Isolation
Power Supply 2 Logic Input Signal Logic Output Signal Power Supply Ground 1 Power Supply Ground 2 Logic Output Enable (Single Channel), Active Low Not Connected
VDD2 VOE OUT1 GND2
Truth Table IN1 L H L H VOE L L H H OUT1 L H Z Z
2
7
3
6
4
5
HCPL-9000/0900
Dual Channel
VDD1 IN1 IN2 GND1
1 8
VDD2 OUT1 OUT2 GND2
VDD1 IN1 OUT2 GND1
1
8
VDD2 OUT1 IN2 GND2
2
7
2
Galvanic Isolation
Galvanic Isolation
7
3
6
3
6
4
5
4
5
HCPL-9030/0930
HCPL-9031/0931
Quad Channel
VDD1 GND1 IN1 IN2 IN3 IN4 NC GND1
1 16
VDD2 GND2 OUT1 OUT2 OUT3 OUT4 NC GND2
VDD1 GND1 IN1 IN2 OUT3 OUT4 NC GND1
1
16
VDD2 GND2 OUT1 OUT2 IN3 IN4 NC GND2
VDD1 GND1 IN1 IN2 IN3 OUT4 NC GND1
1
16
VDD2 GND2 OUT1 OUT2 OUT3 IN4 NC GND2
2
15
2
15
2
15
Galvanic Isolation
Galvanic Isolation
4
13
4
13
4
Galvanic Isolation
3
14
3
14
3
14
13
5
12
5
12
5
12
6
11
6
11
6
11
7
10
7
10
7
10
8
9
8
9
8
9
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
3
Package Outline Drawings HCPL-9000, HCPL-9030 and HCPL-9031 Standard DIP Packages
8 7 6 5
0.240 (6.096) 0.260 (6.604)
1
2
3
4
0.370 (9.398) 0.400 (10.160) 0.290 (7.366) 0.310 (7.874)
0.55 (1.397) 0.65 (1.651)
0.120 (3.048) 0.150 (3.810) 0.008 (0.203) 0.015 (0.381) 0.015 (0.381) 0.035 (0.889) 0.030 (0.762) 0.045 (1.143) 0.015 (0.380) 0.023 (0.584) 0.090 (2.286) 0.110 (2.794) 0.045 (1.143) 0.065 (1.651) 0.300 (7.620) 0.370 (9.398)
3 8
DIMENSIONS: INCHES (MILLIMETERS) MIN MAX
HCPL-9000, HCPL-9030 and HCPL-9031 Gull Wing Surface Mount Option 300
PAD LOCATION (for reference only) 0.370 (9.400) 0.390 (9.900)
8 7 6 5
0.040 (1.016) 0.047 (1.194) 0.190 TYP. (4.826) 0.240 (6.100) 0.260 (6.600) 0.370 (9.398) 0.390 (9.906)
1
2
3
4
0.047 (1.194) 0.070 (1.778) 0.045 (1.143) 0.065 (1.651) 0.370 (9.400) 0.390 (9.900) 0.290 (7.370) 0.310 (7.870)
0.015 (0.381) 0.025 (0.635)
0.030 (0.762) 0.045 (1.143)
0.120 (3.048) 0.150 (3.810)
0.008 (0.203) 0.013 (0.330)
0.030 (0.760) 0.056 (1.400) 0.100 (2.540) BSC DIMENSIONS INCHES (MILLIMETERS) 0.025 (0.632) 0.035 (0.892)
0.015 (0.385) 0.035 (0.885)
12 NOM.
MIN MAX LEAD COPLANARITY = 0.004 INCHES (0.10 mm)
4
HCPL-0900, HCPL-0930 and HCPL-0931 Small Outline SO-8 Package
0.189 (4.80) 0.197 (5.00) 8 0.228 (5.80) 0.244 (6.20) 7 6 5 0.150 (3.80) 0.157 (4.00)
1
2
3
4
0.013 (0.33) 0.020 (0.51) 0.010 (0.25) 0.020 (0.50) x 45 0.054 (1.37) 0.069 (1.75) 0.040 (1.016) 0.060 (1.524) 0.004 (0.10) 0.010 (0.25) 0 8 0.016 (0.40) 0.050 (1.27)
0.008 (0.19) 0.010 (0.25)
DIMENSIONS: INCHES (MILLIMETERS) MIN MAX
HCPL-900J, HCPL-901J and HCPL-902J Wide Body SOIC-16 Package
0.397 (10.084) 0.413 (10.490)
8 1
Pin 1 indent
0.394 (10.007) 0.419 (10.643)
0.291 (7.391) 0.299 (7.595)
0.013 (0.330) 0.020 (0.508)
7 TYP
0.080 (2.032) 0.100 (2.54) 0.040 (1.016) 0.060 (1.524)
0.092 (2.337) 0.104 (2.642) 7 TYP
0.287 (7.290) 0.297 (7.544)
0.010 (0.254) x 45 0.020 (0.508) 0 - 8 TYP
0.004 (0.1016) 0.011 (0.279)
0.009 (0.229) 0.012 (0.305)
0.016 (0.40) 0.050 (1.27)
DIMENSIONS: INCHES (MILLIMETERS) MIN MAX
5
HCPL-090J, HCPL-091J and HCPL-092J Narrow Body SOIC-16 Package
0.386 (9.802) 0.394 (9.999)
8 1
Pin 1 indent
0.228 (5.791) 0.244 (6.197)
0.152 (3.861) 0.157 (3.988)
0.013 (0.330) 0.020 (0.508)
0.054 (1.372) 0.068 (1.727) 0.050 (1.270) 0.060 (1.524) 0.040 (1.016) 0.060 (1.524)
0.008 (0.191) 0.010 (0.249)
0.010 (0.245) x 45 0.020 (0.508) 0 - 8 TYP
0.004 (0.102) 0.010 (0.249)
0.016 (0.406) 0.050 (1.270)
DIMENSIONS: INCHES (MILLIMETERS) MIN MAX
Package Characteristics Parameter
Capacitance (Input-Output) Single Channel Dual Channel Quad Channel Thermal Resistance 8-Pin PDIP 8-Pin SOIC Package Power Dissipation 8-Pin PDIP 8-Pin SOIC
[1]
Symbol
CI-O
Min.
Typ.
1.1 2.0 4.0
Max.
Units
pF
Test Conditions
f = 1 MHz
JCT 150 240 PPD 150 150
C/W
Thermocouple located at center underside of package
mW
Notes: 1. Single and dual channels device are considered two-terminal devices: pins 1-4 shorted and pins 5-8 shorted. Quad channel devices are considered two-terminal devices: pins 1-8 shorted and pins 9-16 shorted. This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure.
6
Insulation and Safety Related Specifications Parameters
Barrier Impedance Single Channel Dual Channel Quad Channel Creepage Distance (External) 8-Pin PDIP 8-Pin SOIC 16-Pin SOIC Narrow Body 16-Pin SOIC Wide Body Leakage Current 240 VRMS 60 Hz 7.036 4.026 4.026 8.077 0.2 A >1014 ||3 >1014 ||3 >1014 ||7 mm
Condition
Min.
Typ.
Max.
Units
||pF
Absolute Maximum Ratings Parameters
Storage Temperature Ambient Operating Supply Voltage Input Voltage Voltage Output Enable (HCPL-9000/-0900) Output Voltage Output Current Drive Lead Solder Temperature (10s) ESD 2 kV Human Body Model Temperature [1]
Symbol
TS TA VDD1, VDD2 VIN VOE VOUT IOUT
Min.
-55 -55 -0.5 -0.5 -0.5 -0.5
Max.
175 125 7 VDD1 +0.5 VDD2 +0.5 VDD2 +0.5 10 260
Units
C C V V V V mA C
Notes: 1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not guarantee performance.
Recommended Operating Conditions Parameters
Ambient Operating Temperature Supply Voltage Logic High Input Voltage Logic Low Input Voltage Input Signal Rise and Fall Times
Symbol
TA VDD1, VDD2 VIH VIL tIR, tIF
Min.
-40 3.0 2.4 0
Max.
100 5.5 VDD1 0.8 1
Units
C V V V s
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure.
7
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA=+25C, VDD1 = VDD2 = +3.3 V.
Parameter
Quiescent Supply Current 1 HCPL-9000/-0900 HCPL-9030/-0930 HCPL-9031/-0931 HCPL-900J/-090J HCPL-901J/-091J HCPL-902J/-092J Quiescent Supply Current 2 HCPL-9000/-0900 HCPL-9030/-0930 HCPL-9031/-0931 HCPL-900J/-090J HCPL-901J/-091J HCPL-902J/-092J Logic Input Current Logic High Output Voltage
Symbol
IDD1
Min.
Typ.
0.008 0.008 1.5 0.016 3.3 1.5
Max.
0.01 0.01 2.0 0.02 4.0 2.0
Units Test Conditions
mA VIN = 0V
IDD2 3.3 3.3 1.5 5.5 3.3 3.0 IIN VOH -10 VDD2 - 0.1 0.8 * VDD2 VDD2 VDD2 - 0.5 0 0.5 0.1 0.8 4.0 4.0 2.0 8.0 4.0 6.0 10
mA
VIN = 0V
A V V V V IOUT = -20 A, VIN = VIH IOUT = -4 mA, VIN = VIH IOUT = 20 A, VIN = VIL IOUT = 4 mA, VIN = VIL
Logic Low Output Voltage
VOL
Switching Specifications
Maximum Data Rate Clock Frequency Propagation Delay Time to Logic Low Output Propagation Delay Time toLogic High Output Pulse Width Pulse Width Distortion [1] |tPHL - tPLH| Propagation Delay Skew [2] Output Rise Time (10 - 90%) Output Fall Time (10 - 90%) tPSK tR tF 4 2 2 3 3 3 3 2 15 18 6 4 4 5 5 5 5 3 ns ns ns ns ns ns ns ns kV/s Vcm = 1000V fmax tPHL tPLH tPW |PWD| 10 2 3 12 12 100 110 50 18 18 MBd MHz ns ns ns ns CL = 15 pF
Propagation Delay Enable to Output (Single Channel) High to High Impedance tPHZ Low to High Impedance High Impedance to High High Impedance to Low Channel-to-Channel Skew (Dual and Quad Channels) Common Mode Transient Immunity (Output Logic High or Logic Low) [3] tPLZ tPZH tPZL tCSK |CMH| |CML|
Notes: 1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width. 2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25C. 3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure.
8
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA=+25C, VDD1 = VDD2 = +5.0 V.
Parameter
Quiescent Supply Current 1 HCPL-9000/-0900 HCPL-9030/-0930 HCPL-9031/-0931 HCPL-900J/-090J HCPL-901J/-091J HCPL-902J/-092J Quiescent Supply Current 2 HCPL-9000/-0900 HCPL-9030/-0930 HCPL-9031/-0931 HCPL-900J/-090J HCPL-901J/-091J HCPL-902J/-092J Logic Input Current Logic High Output Voltage
Symbol
IDD1
Min.
Typ.
0.012 0.012 2.5 0.024 5.0 2.5
Max.
0.018 0.018 3.0 0.036 6.0 3.0
Units Test Conditions
mA VIN = 0V
IDD2 5.0 5.0 2.5 8.0 5.0 6.0 IIN VOH -10 VDD2 - 0.1 0.8 * VDD2 VDD2 VDD2 - 0.5 0 0.5 0.1 0.8 6.0 6.0 3.0 12.0 6.0 9.0 10
mA
VIN = 0V
A V V V V IOUT = -20 A, VIN = VIH IOUT = -4 mA, VIN = VIH IOUT = 20 A, VIN = VIL IOUT = 4 mA, VIN = VIL
Logic Low Output Voltage
VOL
Switching Specifications
Maximum Data Rate Clock Frequency Propagation Delay Time to Logic Low Output Propagation Delay Time to Logic High Output Pulse Width Pulse Width Distortion [1] |tPHL - tPLH| Propagation Delay Skew [2] Output Rise Time (10 - 90%) Output Fall Time (10 - 90%) fmax tPHL tPLH tPW |PWD| tPSK tR tF 10 2 4 1 1 3 3 3 3 2 15 18 3 6 3 3 5 5 5 5 3 10 10 100 110 50 15 15 MBd MHz ns ns ns ns ns ns ns ns ns ns ns ns kV/s Vcm = 1000V CL = 15 pF
Propagation Delay Enable to Output (Single Channel) High to High Impedance tPHZ Low to High Impedance High Impedance to High High Impedance to Low Channel-to-Channel Skew (Dual and Quad Channels) Common Mode Transient Immunity (Output Logic High or Logic Low) [3] tPLZ tPZH tPZL tCSK |CMH| |CML|
Notes: 1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width. 2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25C. 3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure.
9
Applications Information Power Consumption The HCPL-90xx and HCPL-09xx CMOS digital isolators achieves low power consumption from the manner by which they transmit data across isolation barrier. By detecting the edge transitions of the input logic signal and converting this to a narrow current pulse, which drives the isolation barrier, the isolator then latches the input logic state in the output latch. Since the current pulses are narrow, about 2.5 ns wide, the power consumption is independent of mark-to-space ratio and solely dependent on frequency. The approximate power supply current per channel is: I(Input) = 40(f/fmax)(1/4) mA where f = operating frequency, fmax = 50 MHz.
Signal Status on Start-up and Shut Down To minimize power dissipation, the input signals to the channels of HCPL-90xx and HCPL-09xx digital isolators are differentiated and then latched on the output side of the isolation barrier to reconstruct the signal. This could result in an ambiguous output state depending on power up, shutdown and power loss sequencing. Therefore, the designer should consider the inclusion of an initialization signal in this start-up circuit. Bypassing and PC Board Layout The HCPL-90xx and HCPL-09xx digital isolators are extremely easy to use. No external interface circuitry is required because the isolators use high-speed CMOS IC technology allowing CMOS logic
to be connected directly to the inputs and outputs. As shown in Figure 1, the only external components required for proper operation are two 47 nF ceramic capacitors for decoupling the power supplies. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. Figure 2 illustrates the recommended printed circuit board layout for the HCPL-9000 or HCPL-0900. For data rates in excess of 10MBd, use of ground planes for both GND1 and GND2 is highly recommended.
VDD1 C1 IN1
1
HCPL-9000 or HCPL-0900
8 C2 7 6 5 GND2 VOE
VDD2
2 NC 3 GND1 4
OUT1
Note: C1, C2 = 47 nF ceramic capacitors
Figure 1. Functional Diagram of Single Channel HCPL-0900 or HCPL-0900.
VDD1
HCPL-9000 or HCPL-0900
VDD2 VOE C2 OUT1 GND2
IN1 C1
GND1
Figure 2. Recommended Printed Circuit Board Layout.
10
Propagation Delay, Pulse Width Distortion and Propagation Delay Skew Propagation Delay is a figure of merit, which describes how quickly a logic signal propagates through a system as illustrated in Figure 3. The propagation delay from low to high, tPLH , is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low, tPHL, is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low.
Pulse Width Distortion, PWD, is the difference between tPHL and tPLH and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20 - 30% of the minimum pulse width is tolerable. Propagation Delay Skew, tPSK, and Channel-to-Channel Skew, tCSK, are critical parameters to consider in parallel data transmission applications where synchronization of signals on parallel data lines is a concern.
If the parallel data is being sent through channels of the digital isolators, differences in propagation delays will cause the data to arrive at the outputs of the digital isolators at different times. If this difference in propagation delay is large enough, it will limit the maximum transmission rate at which parallel data can be sent through the digital isolators. tPSK is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, among two or more devices which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). tCSK is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, among two or more channels within a single device (applicable to dual and quad channel devices) which are operating under the same conditions. As illustrated in Figure 4, if the inputs of two or more devices are switched either ON or OFF at the same time, tPSK is the difference between the minimum propagation delay, either tPLH or tPHL, and the maximum propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK, can determine the maximum parallel data transmission rate. Figure 5 shows the timing diagram of a typical parallel data transmission application with both the clock and data lines being sent through the digital isolators. The figure shows data and clock signals at the inputs and outputs of the digital isolators. In this case, the data is clocked off the rising edge of the clock.
INPUT VIN tPLH OUTPUT VOUT 90% 10% tPHL 90%
5 V CMOS 50% 0V
10%
VOH 2.5 V CMOS VOL
Figure 3. Timing Diagrams to Illustrate Propagation Delay, tPLH and tPHL.
VIN
50%
INPUTS
DATA
VOUT
2.5 V CMOS tPSK
CLOCK
DATA
VIN
50%
OUTPUTS CLOCK
tPSK
tPSK
VOUT
2.5 V CMOS
Figure 5. Parallel Data Transmission. Figure 4. Timing Diagrams to Illustrate Propagation Delay Skew.
11
Propagation delay skew represents the uncertainty of where an edge might be after being sent through a digital isolator. Figure 5 shows that there will be uncertainty in both the data and clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of
the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through digital isolators in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to
ensure that any additional uncertainty in the rest of the circuit does not cause a problem. Figure 6 shows the minimum pulse width, rise and fall time, and propagation delay enable to output waveforms for HCPL-9000 or HCPL-0900.
50%
VIN
tPZL
90%
90%
tPLZ
50%
VOUT
tPW
tPZH tF
10%
10%
tPHZ
tR
VOE
tPW tPLZ tPZH
Minimum Pulse Width Propagation Delay, Low to High Impedance Propagation Delay, High Impedance to High
tPHZ tPZL tR tF
Propagation Delay, High to High Impedance Propagation Delay, High Impedance to Low Rise Time Fall Time
Figure 6. Timing Diagrams to Illustrate the Minimum Pulse Width, Rise and Fall Time, and Propagation Delay Enable to Output Waveforms for HCPL-9000 or HCPL-0900.
www.agilent.com/semiconductors
For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (408) 654-8675 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6271 2451 India, Australia, New Zealand: (+65) 6271 2394 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6271 2194 Malaysia, Singapore: (+65) 6271 2054 Taiwan: (+65) 6271 2654 Data subject to change. Copyright (c) 2002 Agilent Technologies, Inc. October 31, 2002 5988-5626EN

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